Power MOSFETs (metal oxide semiconductor field effect transistors) are well known in the semiconductor industry. One variety of power MOSFETs is the vertically-conducting trench MOSFET. A cross-section view of such a MOSFET is shown in FIG. 1, wherein MOSFET 100 has trenches 106 each including a poly-silicon gate 108 insulated from body regions 110 by a gate dielectric 112; source regions 114 flank each side of the trenches 106; dielectric layer 116 insulates the gates 108 from an overlay metal layer 118; and substrate region 102 forms the drain of MOSFET 100.
When MOSFET 100 is in the on state, current flows vertically between the source regions 114 and the substrate 102; and the current is a function of the drain to source resistance (Rdson). To improve the current capability of the MOSFET, it is very effective to reduce the Rdson. One way to reduce the Rdson of the trench MOSFET is to increase the trench density (i.e., to increase the number of trenches per unit area), and this can be achieved by reducing the cell pitch. However, reducing the cell pitch of MOSFETs is limited not only by the MOSFET cell structure but also the specific process to fabricate the MOSFET. Furthermore, reducing the cell pitch is made further difficult by the limitations of the manufacturing process technology such as the minimum critical dimensions that the lithography tools can achieve, the minimum required spacing between different cell regions as dictated by the design rules, and the misalignment tolerances.
The different dimensions that determine the minimum cell pitch for trench MOSFET 100 are shown in FIG. 1. Dimension A is the minimum trench width that the lithography tools can achieve, dimension B is the minimum contact opening that the lithography tools can achieve, dimension C is the minimum trench-to-contact spacing dictated by the design rules, and dimension D is the contact registration error tolerance or contact misalignment tolerance. The minimum cell pitch for MOSFET 100 thus equals A+B+2C+2D. Reducing any of these dimensions without complicating the process technology is difficult to achieve.
As MOSFET shrinks smaller and smaller, a small misalignment will cause a large variation of trench-to-contact spacing variation, and it will affect the device parameters dramatically. Moreover, to make the threshold voltage of MOSFET easy for modeling, smaller contact opening dimension, which affects the threshold voltage significantly, is required. By shrinking the contact opening dimension, parasitic capacitance can be reduced, and the threshold voltage will be controlled more precisely as well.
The document U.S. Pat. No. 7,344,943 disclosed a method using an exposed edge of an insulating layer in each trench to define a portion of each contact opening between every two adjacent trenches.
The document U.S. Pat. No. 7,375,029 disclosed a method fabricating contact openings in mesa regions of a semiconductor body.
The document U.S. Pat. No. 6,277,695 disclosed a method to form a self-aligned contact opening in a vertical planar DMOSFET (double-diffused MOSFET) by forming spacers on the sides of a gate section.
Although the documents described above have raised different methods to form a self-aligned contact opening, they are only suitable for either the gate is underneath the top surface of the substrate or the gate is above the top surface of the substrate. Moreover, they are still insufficient to control the contact opening dimension very precisely. Therefore, there is a need for a contact opening process no matter whether the gate is underneath the top surface of the substrate or the gate is above the top surface of the substrate to reduce the cell pitch, moreover, the contact opening dimension and the contact misalignment tolerance of trench MOSFET can be precisely controlled without increasing the process complexity.